¶ LiveBench for the Evaluation of Cascade2 SiT95316EB (SiT95x chip designs)
¶ Contents
Introduction to Cascade SiT6503EB (SiT9514x designs)
- Lab Setup
- Key Features
- Applications
- Test Outputs
- Document links
¶ Introduction to Cascade SiT95316EB :
The SiT95316EB Programmer is designed exclusively to configure and burn programmable SiT9514x Cascade Platform™ units.SiT95211 and SiT95316 are programmable clock generator parts with flexible input-output frequency translation options. They feature an ultra-low jitter performance DPLL that supports up to 4 Diff/8 Single Ended input clocks and 12 clock outputs. These parts can be derived from any of the four PLLs in a flexible manner.
¶ SiT95211
¶ Ultra Low Jitter, Programmable Frequency, 12 Outputs Quad PLL Clock Generator:
SiT95211 provides programmable clock generator parts based on Quad Fractional Frequency Translation with a variety of input to output frequency translation options. With 12 clock outputs and up to 4 Diff/8 Single Ended input clocks that are shared by all 4 fractional translations, the ultra low jitter performance DPLL is supported. There is complete flexibility in deriving the clock outputs from any one of the four PLLs. SiT95211 is a QFN package measuring 9x9 mm. It can be fully programmed using the I2C/SPI interface or, for devices that are already pre-programmed from the factory, an on-chip one-time programmable non-volatile memory.
Documentation:
¶ SiT95210
¶ Low Jitter, Quad PLL, 4-output Clock Generator:
The SiT95210 clock generator features programmable quad fractional frequency translation with jitter cleaning and flexible input-to-output frequency translation options. Its ultra-high-performance PLLs support up to 4 differential or 8 single-ended input clocks, shared across all 4 fractional translations, and deliver 4 configurable clock outputs. These outputs can be flexibly sourced from any of the 4 PLLs. The device is fully programmable via an I2C/SPI interface or an on-chip one-time programmable (OTP) non-volatile memory, allowing for factory pre-programmed configurations.
Documentation:
¶ SiT95314
¶ Quad PLL, 4-output Jitter Cleaner:
The SiT95314 jitter cleaner delivers advanced programmable quad fractional frequency translation with robust jitter cleaning capabilities and versatile input-to-output frequency translation options. It features high-performance PLLs that support up to 4 differential or 8 single-ended input clocks, along with 4 configurable clock outputs. These outputs can be flexibly sourced from any of the 4 PLLs. The device is fully customizable through an I2C/SPI interface or an on-chip one-time programmable (OTP) non-volatile memory, enabling factory pre-programmed configurations.
Documentation:
¶ SiT95315
¶ Quad PLL, 12-output Jitter Cleaner:
The SiT95315 provides advanced programmable quad fractional frequency translation with jitter cleaning and flexible input-to-output frequency translation capabilities. Its high-performance DPLLs support up to 4 differential or 8 single-ended input clocks and deliver 12 configurable clock outputs. These outputs can be flexibly sourced from any of the 4 PLLs. The device offers full programmability via an I2C/SPI interface or an on-chip one-time programmable (OTP) non-volatile memory, allowing for factory pre-programmed configurations.
Documentation:
¶ SiT95316
¶ Quad PLL Frequency Translator / Network Synchronizer:
SiT95316 provides jitter cleaning clock synthesizer components that are based on programmable quad fractional frequency translation with customizable input to output frequency translation choices. 12 clock outputs are provided by the ultra-high performance DPLL, which allows up to 4 Diff/8 Single Ended input clocks that are shared by all 4 fractional translations. Any of the four PLLs can be used to generate the clock outputs in a completely customizable way. SiT95316 is packaged in a QFN 9x9 mm size. For devices that have already been pre-programmed by the manufacturer, it can be fully programmed using the I2C/SPI interface or an on-chip one-time programmable non-volatile memory.
Documentation:
¶ SiT95317
¶ Quad PLL, 12-output Network Synchronizer:
The SiT95317 network synchronizer delivers programmable quad fractional frequency translation with versatile input-to-output frequency translation options. Equipped with high-performance DPLLs, it supports up to 4 differential or 8 single-ended input clocks and provides 8 configurable clock outputs. These outputs can be flexibly sourced from any of the 4 PLLs. The device is fully programmable via an I2C/SPI interface or an on-chip one-time programmable (OTP) non-volatile memory, enabling factory pre-programmed configurations.
Documentation:
¶ Lab Setup :
¶ Key Features :
- Ultra-high Performance PLLs
- Fully Integrated design with no external components
- Sub 70fs Typical RMS integrated jitter (12k-20M)
- Fully Flexible Output and Input Mux: High level of flexibility in output allocation for PLLs
- JESD204B/C Support for data converter clocks
- Frequency Control DCO: DCO Control on all outputs(down to 0.001 ppt)
- Phase Control DCO: Fine phase adjustment knob for phase of all outputs from a PLL (adjustment accuracy < 1ps) in both closed loop and open loop modes
- Repeatable input to output delays with output relative delay adjust
- Internal ZDB Mode with < 0.5 ns Input to Output delay variation. Independently available for each PLL
- Outputs can be phase aligned on independent sync pulse
- External EEPROM Support
- 122.88M Output with excellent close in noise performance
- 64 QFN 9 mm x 9 mm Package
¶ Applications :
- Carrier Ethernet,
- OTN Equipment,
- Microwave Backhaul,
- Gigabit Ethernet,
- Wireless Infrastructure,
- Network Line Cards,
- Small Cells,
- Data Center/Storage,
- SONET/SDH,
- Test / Instrumentation,
- Broadcast Video
¶ Test Outputs:
- This design provides a provision for users to analyze the jitter and phase noise in signals configured for different chip selections as mentioned above for SiT95316.
- The user can observe the output response of the signal collected from the phase noise analyzer and look into the summary file data for quick comparison.
- The user can perform phase noise analysis for MEMS Clock generators, MEMS Jitter Cleaner, and MEMS Network Synchronizers.
- The UI provides an option for users to download the analysis data for future reference.
¶ Document Links :
Link to product page : click here
Product purchase link : click here